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1. general description the uba2013/l3 is a high voltage ic intended to drive and control fluorescent lamps. the ic can handle both cold and warm ignition of the lamp. it contains a t on -controlled pfc function, a half bridge controller circuit with level shifter and an internal bootstrap diode to drive an external half bridge. uba2013/l3 also offers a functionality to properly handle fault conditions such as capacitive mode switching, end-of-lamp-life and overcurrent. uba2013/l3 is designed for wide-input ma ins voltage (120 v - 277 v) applications. 2. features 2.1 half bridge 2.2 pfc 3. applications the uba2013/l3 can provide the drive and contro l function for a wide range of half bridge based ballast applications at different mains voltages. 4. ordering information uba2013/l3 hb driver ic with pf c for fluorescent rings rev. 00.01 ? 23 february 2007 preliminary data sheet ? suitable for cold and warm ignition ? adjustable preheat current ? adjustable preheat time ? single ignition attempt ? adjustable ignition voltage ? automatic restart after relamping ? integrated boot strap function ? protection for capacitive mode ? protection for lamp failure and end-of-life ? three pin pfc controller using t on control ? overvoltage/overcurrent protection ? critical mode operation table 1. ordering information type number package name description version uba2013t so16 plastic small outline package; 16 leads; body width 3.9mm sot109-1 free datasheet http:///
5. block diagram fig 1. block diagram of uba2013/l3 bootstrap level- shifter high side driver non- overlap supply bandgap low side driver timing stop rs mon eol oscillator control pfc fs g1 s1 g2 cp sto p rs eol vdd g zcd vo ovc rref cf ci gnd uba2013 014aaa042 free datasheet http:///
6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for uba2013/l3 uba2013 vo gzc d ovc gnd cf vdd ci g2 cp rs eol g1 r ref fs s top s1 014aaa044 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description vo 1 pfc output voltage sensing ovc 2 pfc overvoltage/current cf 3 oscillator capacitor ci 4 integrating capacitor cp 5 timing capacitor eol 6 end-of-life rref 7 reference resistor stop 8 stop s1 9 source high side transistor (t1) fs 10 high side floating supply g1 11 gate high side transistor (t1) rs 12 current sensor g2 13 gate low side transistor (t2) vdd 14 low voltage supply gnd 15 ground gzcd 16 pfc gate and zcd free datasheet http:///
7. functional description 7.1 start-up state initial start up can be achieved by means of charging the vdd low voltage supply capacitor (c2 in the application diagram figure 6 ) via an external start-up resistor. start-up state is one of the non-oscillating sub-st ates. mosfet t2 c onducts and t1 is non-conducting, ensuring bootstra p capacitor c3 to be charged. in this state the circuit will be reset. the gzcd pin is pulled down and i vo(ref) is not active. if v stop < v stop(reset) at the transition of v dd exceeding v dd(start) , the ic will enter the oscillating state. if not it will enter the stop state. 7.2 half bridge oscillator oscillation of the half bridge is controlled by a built-in current-co ntrolled oscillator which generates a sawtooth waveform at the cf pin. the sawtooth frequency is twice the half bridge frequency, and is determined by the capacitor at the cf pin and the current-out of pin cf, as controlled by the voltage at the ci pin. frequency modulation is achieved by charging and discharging the ci capacitor. the ic brings mosfets t1 and t2 alternately into conduction with a duty factor of just below 50% each (except for situations where v rs exceeds v rs(clamp) ). figure 3 represents the timing of the ic. the circuit block ?non-overlap? generates a non-overlap time t no that ensures periods of exclusive conduction of t1 or t2. time t no depends on the reference current i rref . 7.3 oscillating state oscillating state can be entered: ? when in the startup state v stop < v stop(reset) at the moment v dd reaches v dd(start) , ? when in the vddlow state, when v stop < v stop(ref) at the moment v dd reaches v dd(start) . the oscillating state has three sub-states: th e preheat state, the ignition state and the burn state. the circuit always starts oscillating in the preheat state. fig 3. oscillator timing t no t no v cf i nternal clock v g1_s1 v g2 014aaa04 4 free datasheet http:///
7.4 preheat state the circuit starts oscillating at the half-brid ge frequency f start (approximately 2.5 x f b ). the frequency gradually decreases until a user-d efined value of the preheat current is reached. the slope of the decrease in frequency is determined by the capacitor at the ci pin. during preheat, the circuit monitors t he inductor current by measuring the voltage across external resistor rs at the end of the conduction of t2 with decision level v rs(ph) . the frequency is decreased for as long as v rs < v rs(ph) . the frequency is increased for v rs > v rs(ph) . during preheat the stop pin is discharged to ground via a switch with an on resistance of r stop(disch) . the cycle-by-cycle excess charge control mechanism described in the ignition state is not active during the preheat state. the preheat time is determined by capacitor cp. for cold ignition the preheat time can be reduced by choosing a smaller cp capacitor. the circui t can be locked in the preheat state by connecting pin cp to ground. 7.5 ignition state after the preheat time the ignition state is entered and the frequency will sweep down due to charging of the capacitor at the ci pin with the internally fixed current i ci(charge) . during this decrease in frequency, the circuit appr oaches the resonance frequency of the load. this will cause a high voltage across the load, which normally ignites the lamp. in order to limit voltages and currents in the resonant circuit in case of non- or delayed ignition, a cycle-by-cycle excess charge co ntrol mechanism is used to prevent deep saturation and to limit the lamp voltage. when the voltage at pin rs exceeds v rs(clamp) the impedance of the pin changes from essentially infinite to essentially zero. if a current is flowing into pin rs during the on-state of t2, a fraction k isat of that current will be fed into the capacitor c cf at pin cf in addition to the osc illator current alr eady flowing into c cf . the amount of current fed into c cf depends on the voltage across rs and the value of resistor r, see figure 4 . the increased current rapidly (but not instantly) ends the oscillator half-cycle, after which t2 is switched off. the on-time of t1 is not affected and thus the half bridge will run asymmetrically, see figure 4 . free datasheet http:///
7.6 burn state at the end of the ignition time, the burn state is entered. in this state the voltage at the ci pin will continue to increase until a clamp leve l is reached correspo nding to the minimum frequency f b . the circuit will continue to oscillate at the minimum frequency, unless capacitive mode is detected. in the burn state the cp pin is pulled to ground with a discharge impedance r cp(disch) . the eol protection is enabled. the excess charge control mechanism will remain active. 7.7 capacitive mode protection capacitive mode protection is ac tive in all oscillating states. the signal across resistor rs (r6 in the application diagram of figure 6 ) also gives information about the switching behavior of the half bridge. if the voltage across resistor rs is not below v rs(cap) at the moment of turn-on of t2, the capacitive mode detection circuit assumes the circuit to be in capacitive mode. upon capacitive mode detect ion ci is gradually discharged and instantly the frequency gradually increases as long as capacitive mode is detected. the frequency decreases gradually down to the minimum fre quency if no capacitive mode is detected. detecting capacitive mode at the maximum frequency will ac tivate the internal current i stop(ch) that charges the stop pin. 7.8 stop function for all oscillating states the ic will enter the stop state for v stop > v stop(ref) . note that there is no internal stop timing. an external stop timing can be obtained via the rc time of the network r4, r5 and c11, see the application diagram in figure 6 . during preheat the fig 4. excess charge control t2 t1 t2 t1 vcf 014aaa04 5 rs clamp vrs(ph) rs r6 t2 rs k lsat x i rs time free datasheet http:///
stop pin is discharged to ground via a switch with on-resistance r stop(disch) . in case of a vo-low condition (see section 7.15 ), the stop pin is discharged with a current i stop(dis) . apart from the preheat state or a vo-low condition, the ic will not discharge the stop pin at any vdd. 7.9 end-of-life protection the end-of-life circuit is only active in the burn state and consists of a voltage window comparator circuit. it compares the voltage at the eol pin with two internal reference voltages. when the voltage at the eol pin is above v eol(high) or below v eol(low) the ?end-of-life? protection circuit activates the internal current source i stop(ch) that charges the stop pin. the ?end-of-life? protection is not active in case of a vo-low condition (see section 7.15 ). 7.10 non-oscillating state transitions to the non-oscillati ng state are always made during a g2 high condition in the half bridge (lower mosfet t2 conducting). in the n on-oscillating state t1 is off, t2 is on, the pfc control function is st opped by pulling the gzcd pin do wn to ground continuously, and reference current i vo(ref) is switched off. additionally, the cp and ci pins are discharged to ground. th e non-oscillating state has three sub-states: the start-up state, the stop state and the vddlow state. 7.11 start-up state described at the beginning of this functional description. 7.12 stop state the circuit will enter the stop state: ? when in any of the oscillating states v stop > v stop(ref) , ? when in the vddlow state v stop > v stop(ref) at the moment v dd exceeds v dd(start) , ? when in the startup state v stop > v stop(reset) at the moment v dd exceeds v dd(start) . in the stop state, a clamp circuit is acti ve, limiting the voltage at the vdd pin to v dd(clamp) . the ic goes from the stop stat e into the startup state if v dd drops below v dd(reset) . 7.13 vddlow state the circuit will enter vddlow state in any of the o scillating states when v dd drops below v dd(low) . the circuit then goes from vddlow state to: ? the startup state if v dd drops below v dd(reset) , ? the stop state if v stop > v stop(ref) at the moment v dd exceeds v dd(start) , or ? the preheat state if v stop < v stop(ref) at the moment v dd exceeds v dd(start) . free datasheet http:///
7.14 pfc function the internal pfc control block provides a t on controlled, critical mode power factor correction controller. the t on is set by the voltage at the vo pin. the duration of the t on pulse decreases linearly with increasing v vo . the v vo voltage is the result of an error current through the compensation impedance c onnected at the vo pin. this error current is the difference between a current proporti onal to the output voltage of the pfc pulling the vo pin high and an internal reference current i vo(ref) pulling the vo pin low. the external mosfet is primarily driven via the secondary winding on the inductor l p1 . the t on timing starts the moment v gzcd exceeds v gzcd(start) (below the threshold of the external mosfet). the external mosfet is turned on and current builds up in the inductor l p1 . at the end of t on the output driver pulls the gzcd pin down during a defined time t off . this turns off the external mosfet. the inductor current i lp1 now flows through the boost diode dp2. the polarity of the voltage across the secondary winding changes to negative, keeping the external mosfet in the off state. as long as v gzcd is below v gzcd(start) the t on timing is reset. the current in the inductor decreases linearly to below zero. just after the zero crossing the polarity of t he voltage across the secondary winding becomes positive and makes v gzcd exceed v gzcd(start) , starting the t on timing, turning on the external mosfet and completing the cycle. t on varies linearly from t on(max) to t on(min) in the range of v vo from v vo(low) to v vo(low) + ? v vo . above a voltage v vo(off) (>v vo(low) + ? v vo ) at the vo pin, t on is zero and the gzcd pin is continuously pulled down. the ovc pin is intended for over-voltage and/ or over-current protection. the voltage at the ovc pin is compared to a reference voltage v ovc(ref) . for v ovc > v ovc(ref) the gzcd pin is pulled down within a time t ovc . as long as v ovc > v ovc(ref) the gzcd pin will be continuously pulled down by the output driver. additionally, the ovc pin provides protection against an accidental open circuit of the external ovc divider of the pfc output voltage. as long as v ovc < v ovc(low) the gzcd pin is continuously pulled down by the output driver. in order to prevent persist ent ambiguous drive signals for the external mosfet, for v gzcd > v gzcd(start) the gzcd pin is charged after a delay of t gzcd with a current of i gzcd(on) up to a voltage of v gzcd(active) (above the threshold of the ex ternal mosfet). note that the voltage at the gzcd pin is not clamped at v gzcd(active) : the secondary winding on the inductor l p1 can take the gzcd pin up to v dd . the pfc function is self-starting by means of a current source i gzcd(start) (<< i gzcd(on) ) which, under oscillation cond itions, continuously charges the gzcd pi n. in any of the non-oscillating states the current sources i gzcd(start) and i vo(ref) are off and the gzcd pin is continuously pulled down. in oscillating cond itions the positive voltage at the vo pin is clamped at a level v vo(clamp) : in non-oscillating conditions, the positive voltage at the vo pin is clamped at a level < v vo(off) . 7.15 vo-low condition in order to prevent unintended stopping in case of the mains voltage being too low for the pfc stage to maintain its inte nded output voltage, this condition is detected in the oscillating state by the current sunk into the vo pin dropping below k vo *i vo(ref) , where the constant k vo represents a fraction (typ. 95%) of i vo(ref) . in case of a vo-low condition: ? the end-of-life protection is deactivated, free datasheet http:///
? the stop level is effectively raised by discharging the stop pin with a current i stop(dis) . the vo-low condition is overruled when v ovc 8. limiting values [1] in accordance with the human b ody model (hbm): i.e. equivalent to discharging a 100 pf capacitor through a 1.5 k ? series resistor. [2] in accordance with the machine model (mm): i.e. equivalent to discharging a 200 pf capacitor through a 10 ? series resistor and a 0.75 h inductor. table 3. limiting values symbol parameter conditions min max unit v fs high-side floating supply voltage o p e r a t i n g t<0.5s 0 570 630 v v rs voltage at pin rs [3] 0v be v i rs current in pin rs t<1.0 s [4] -10 10 ma v g1 voltage at pin g1 [3] v s1 -v be v fs v v g2 voltage at pin g2 [3] -v be v vdd v v vdd low-voltage supply t<0.5s over lifetime 015v v vdd low-voltage supply in stop state 0 14 v i vdd clamp current in pin vdd 5 ma v gzcd voltage at pin gzcd [3] -v be v vdd v v ovc voltage at pin ovc 0 5 v i vo current in pin vo v vdd = 0v to v vddmax 0 200 a i cf current in pin cf v vdd = 0v to v vddmax 0 200 a i eol current in pin eol v vdd = 0v to v vddmax -1 1 ma sr slew rate at pins s1, g1 and fs with respect to ground -4 4 v/ns t j junction temperature -25 150 c t amb ambient temperature -25 100 c t stg storage temperature -55 150 c v esd(hbm) hbm electrostatic handling voltage pin eol and g1 pins fs, s1, vdd and g2 pins vo, ovc, cf, ci, cp, rref, stop, rs, gzcd [1] <500 1000 2000 v v v v esd(mm) mm electrostatic handling voltage pin eol pins fs, g1, s1, vdd and g2 pins vo, ovc, cf, ci, cp, rref, stop, rs, gzcd [2] 50 100 200 v v v q coupl charge coupling at pins rref and cf operating -8 8 pc r rref reference resistor 22 47 k ? free datasheet http:///
[3] at t amb = 25 c the typical v be is 0.7 v. [4] at negative rs currents (typ. < -5 ma) capacitive-mode protection can be triggered. 9. thermal characteristics 10. characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient so16 in free air 100 k/w r th(j-pin) thermal resistance from junction to pin so16 in free air 50 k/w table 5. characteristics t amb = 25 c; v vdd = 13.0 v; c cf = 100 pf; r rref = 33 k ? ; c cp = 100 nf; c ci = 100 nf; all voltages referenced to ground unless otherwise specified. symbol parameter conditions min typ max unit high-voltage supply i l1 leakage current: high-voltage pins fs, g1, s1 = 630 v, v vdd = 0 v 15 a start-up state v dd(start) start of oscillation 12.1 12.6 13.1 v v dd(low) stop of oscillation 9.7 10.2 10.7 v v dd(hys) start-stop hysteresis 2.2 2.4 2.6 v i vdd(nonosc) non-oscillating current vvdd = 12 v [2] 100 150 200 a v dd(clamp) clamp voltage vdd at 5 ma non-oscillating 10.0 12.0 14.0 v v dd(reset) reset voltage [10] 4.5 5.5 6.5 v preheat voltage f start starting frequency v ci = 0 [1] 101 112.5 124 khz t ph preheat time c cp = 100 nf 574 674 796 ms i cp(charge) charge current at cp pin v cp = 1.0 v 6.0 a i cp(discharge) discharge current at cp pin v cp = 3.5 v 6.0 a ? v cp(pk) peak voltage difference at cp pin when timing 2.45 v v cp(min) cp comparator level low 1.10 1.25 v v rs(ph) control voltage at rs pin [5] 365 400 435 mv ignition state t ig ignition time c cp = 100 nf 512 611 730 ms v rs(clamp) saturation current detection level at i rs(ig) = 0.5 ma 0.75 v k isat saturation contro l current gain [6] 0.45 0.50 0.55 a/a burn state f b bottom frequency [1] 43.6 45.0 46.4 khz t no non-overlap time 1.05 1.40 1.75 s sym f b symmetry half bridge [1] [9] 0.9 1.0 1.1 sym t no symmetry non-overlap time [11] 1.0 free datasheet http:///
i tot total supply current [1] [7] 1.5 2.0 ma i ci(charge) charge current at ci pin v ci = 1.5 v 36 44 52 a i ci(discharge) discharge current at ci pin v ci = 1.5 v 74 90 106 a ? i cf / ? v ci ci transconductance v ci = 1.5 v 12 a/v v rs(cap) capacitive-mode control voltage [8] -40 -20 0 mv v rref reference voltage 2.425 2.500 2.575 v v g1(on) on voltage at pin g1 |i g1 | = 1 ma 10.5 v v g1(off) off voltage at pin g1 |i g1 | = 1 ma 0.3 v vg2(on) on voltage at pin g2 |i g2 | = 1 ma 10.5 v vg2(off) off voltage at pin g2 |i g2 | = 1 ma 0.3 v r g1(on) high side driver on resistance v (g1-s1) = 3 v 250 ? r g1(off) high side driver off resistance v (g1-s1) = 3 v 35 ? r g2(on) low side driver on resistance v g2 = 3 v 250 ? r g2(off) low side driver off resistance v g2 = 3 v 35 ? v drop voltage drop at bootstrap switch i fs = 5 ma 2.0 v r cp(disch) on resistance switch at cp pin v cp = 0.6 v 120 ? stop and end-of-life v stop(ref) stop reference level 1.21 1.26 1.31 v v stop(reset) stop reset level [10] 0.95 1.00 1.05 v v stop(hys) stop hysteresis [10] 0.20 0.25 0.30 v i stop(ch) stop-charge current source v stop = 0.75 v 2.0 2.5 3.0 a i stop(dis) stop discharge current v stop = 0.75 v 0.35 0.50 0.65 a r stop(disch) on resistance discharge switch v stop = 0.5 v 1.0 2.5 4.0 k ? v eol(high) high level end-of-life comparator 2.9 3.0 3.1 v v eol(low) low level end-of-life comparator 1.9 2.0 2.1 v power-factor control i vo(ref) output voltage reference current v vo = 3.0 v 97 102 107 a v ovc(ref) ovc reference le vel 1.21 1.26 1.31 v t ovc delay ovc comparator 60 ns v vo(low) vo offset voltage 1.0 v ? v vo vo dynamic range 2.7 v i gzcd(start) start-up current at gzcd pin v gzcd = 0 v 35 42.5 50 a i gzcd(on) turn on current at gzcd pin v gzcd = 3 v 12 a v gzcd(start) gzcd start level 1.9 2.0 2.1 v v gzcd(active) gzcd active level i gzcd = 0.5 ma 6.4 v t gzcd gzcd turn on delay 0.5 s t on(max) maximum on time v vo = v vo(low) [4] 20 s t on(min) minimum on time v vo = v vo(off) [3] [10] 0.4 0.5 s i gzcd(sink) gate drive sink current v gzcd = 4 v 200 ma table 5. characteristics ?continued t amb = 25 c; v vdd = 13.0 v; c cf = 100 pf; r rref = 33 k ? ; c cp = 100 nf; c ci = 100 nf; all voltages referenced to ground unless otherwise specified. symbol parameter conditions min typ max unit free datasheet http:///
[1] excluding situations where the excess charge control mec hanism is active. [2] the non-oscillation current is specifi ed in a temperature range of 0 to 100 c. for tj < 0 c and tj > 100 c the maximum start-up current is 350 a. [3] minimum on-time is defined without the external mosfet. v gzcd is increased from 0 to 10 v in 1 s. t onmin is defined as the time elapsed between v gzcd exceeding v gzcd(start) and v gzcd being pulled below 3 v at turn-off. [4] maximum on-time is defined without the exte rnal mosfet. parameter is measured with v vo = v vo(low) and v gzcd is increased from 0 to 10 v in 1 s. t onmax is defined as the time elapsed between v gzcd exceeding v gzcd(start) and v gzcd pulled below 3 v at turn- off. [5] data sampling of v rs(ph) is performed at the end of conduction of t2 . [6] gain is defined as i cf /i rs with v rs >v rs(clamp) . [7] total supply current is specified in a t j temperature range of -20 c to 125 c at f b , excluding gate drive charge. [8] data sampling of v rs(cap) is performed at the start of conduction of t2 . [9] the symmetry sym f b is calculated from the quotient sym f b = t1 tot /t2 tot , with t1 tot being the time between turn-off of g2 and the turn-off of g1, and t2 tot the time between turn-off of g1 and the turn-off of g2. [10] not measured, guaranteed by design. [11] the symmetry sym t no is defined as the ratio between deadtime1 and deadtime2. deadtime1 is the time between turning off g1 and turning on g2. deadtime2 is the time between turning off g2 and turning on g1. 11. latch-up [1] negative latch-up currents tested at t j = 150 c by discharging a 22 mf capacitor through a 50 ? series resistor. positive latch-up currents according to quality specification. t off duration off pulse 0.9 s v ovc(low) ovc low voltage 120 mv k vo vo low factor 0.86 0.95 0.99 v vo(off) off voltage pfc 3.7 v v vo(clamp) active vo clamp voltage i vo = 200 a4.7v v vo(pas) passive vo clamp voltage i vo = 200 a, v vdd = 0 v 3.9 v table 5. characteristics ?continued t amb = 25 c; v vdd = 13.0 v; c cf = 100 pf; r rref = 33 k ? ; c cp = 100 nf; c ci = 100 nf; all voltages referenced to ground unless otherwise specified. symbol parameter conditions min typ max unit table 6. latch-up (positive currents flow into pins) symbol parameter conditions min unit i latch up latch-up current [1] pin rs [1] -30 ma pin cf [1] -50 ma pin stop [1] -80 ma pins vo, ovc, ci, cp, eol, rref, stop, s1, fs, g1, g2, gzcd [1] -100 ma free datasheet http:///
12. application information fig 6. application diagram of UBA2013L/3 bootstrap level- shifter high side driver non- overlap supply bandgap low side driver timing stop rs mon eol oscillator control pfc fs g1 s1 g2 cp stop rs eol vdd gzcd vo ovc rref cf ci gnd uba2013 014aaa047 dp1 dp2 lp1 cp2 d1 d2 rp1 rp2 rp 4 rp 7 rp 5 rp 8 c1 c2 cp1 tp1 rp4 dp3 d3 d4 rp 3 cp 3 rp 6 cp 4 r3 c5 c6 ic1 r6 c15 r8 c14 r9 c11 r5 d6 c10 r4 r7 c4 r2 c 12 c9 t2 z1 c7 c8 t1 d5 r 1 l1 c13 c3 m ains free datasheet http:///
12.1 design equations equation 1 through equation 5 give the design equations for the uba2013: bottom frequency fb is set by rref and cf: (1) preheat time tpreh is set by rref and cp: (2) ignition time tign is set by rref and cp: (3) non-overlap time tno is set by rref: (4) pfc on-time ton: (5) 13. test information the general quality specification for integrated circuits snw-fq-611-e is applicable. table 7. uba2013 parameters (typical) x1 = 3.24 rint = 3 k ? t = 300ns cpar = 5 pf (typ) f b 1 2c cf c par + () x1 r rref r int ? () [] + {} --------------------------------------------------------------------------------------------------------------------- - hz () = t preh 674 c cp 100 nf --------------- - r rref 33 k ? --------------- ms () = t ign 611 c cp 100nf --------------- - r rref 33k ? --------------- ms () = t no 0.15 1.25 r rref 33k ? --------------- s () + = t on v vo () t on max () t on max () t on min () ? () ? v vo ------------------------------------------------------ v vo v vo low () ? () ? = free datasheet http:///
14. package outline fig 7. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale s o16: plastic small outline package; 16 leads; body width 3.9 mm sot109 -1 free datasheet http:///
draft draft draft dr draft draft draft dr af draft draft dr aft draft dra f t d draft draft draft draft dr aft draft dra xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x UBA2013L_1 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 00.01 ? 23 february 2007 17 of 22 nxp semiconductors uba2013/l3 hb driver ic 15. appendix 15.1 state diagram and state transitions fig 8. state diagram and state transitions stop (sub) state stop state characteristics: - vddclamp (12v) active vdd < vddreset (5v) vdd > vddstart (12.6v) and vcstop > vstopreset (1.0v) vdd > vddstart (12.6v) and vcstop > vstopref (1.25v) startup (sub) state vddlow (sub) state non-oscillating state general non-oscillating state characteristics: - t2 on, t1 & tup off - current sources ivoref and igzcdstart off - reset oscillating-state counters and latches - discharge ci- and cp-pin to gnd vdd < vddreset (5v) oscillating state general oscillating state characteristics: - pfc active, incl. current sources ivoref and igzcd start - capactive mode detection active (vrs -20mv comp) - cap. mode and fmax ==> charge stop pin with istopch (2.5ua) - vo-low ==> discharge stop pin with istopdis (0.5ua) n.b.: istopch and istopdis can flow simulaneously burn state characteristics: - excess charge control active - eol and not vo-low ==> charge - stop pin with istopch (2.5ua) - discharge cp to gnd burn state ignition state characteristics: - cp timing - excess charge control active ignition state preheat state characteristics: - upon entry: t=0, f=fmax - cp timing - vrspreh (400mv) comp active - discharge stop pin preheat state t=tign t=tpreh vcstop > vstopref (1.25v) and g2=high vdd < vddlow (10.0v) and g2=high vdd > vddstart (12.6v) and vcstop < vstopref (1.25v) vdd > vddstart (12.6v) and vcstop < vstopreset (1.0v ) 014aaa04 8 free datasheet http:///
16. revision history table 8. revision history document id release date data sheet status change notice supersedes UBA2013L_1 obje ctive data sheet - - free datasheet http:///
draft draft draft dr draft draft draft dr af draft draft dr aft draft dra f t d draft draft draft draft dr aft draft dra UBA2013L_1 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 00.01 ? 23 february 2007 19 of 22 nxp semiconductors uba2013/l3 hb driver ic 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liabili ty for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. 17.4 licenses 17.5 patents notice is herewith given that the subj ect device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions. ? owned by 17.6 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. ? is a trademark of nxp b.v. 18. contact information for additional information, please visit: http://www.nxp.com for sales office addresses, send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. purchase of nxp components free datasheet http:///
draft draft draft dr draft draft draft dr af draft draft dr aft draft dra f t d draft draft draft draft dr aft draft dra UBA2013L_1 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 00.01 ? 23 february 2007 20 of 22 continued >> nxp semiconductors uba2013/l3 hb driver ic 19. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 table 3. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4. thermal characteristics . . . . . . . . . . . . . . . . . . 11 table 5. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7. uba2013 parameters (typical) . . . . . . . . . . . . .15 table 8. revision history . . . . . . . . . . . . . . . . . . . . . . . .18 free datasheet http:///
draft draft draft dr draft draft draft dr af draft draft dr aft draft dra f t d draft draft draft draft dr aft draft dra UBA2013L_1 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 00.01 ? 23 february 2007 21 of 22 continued >> nxp semiconductors uba2013/l3 hb driver ic 20. figures fig 1. block diagram of uba2013/l3 . . . . . . . . . . . . . . . .2 fig 2. pin configuration for uba2013/l3 . . . . . . . . . . . . .3 fig 3. oscillator timing . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 4. excess charge control . . . . . . . . . . . . . . . . . . . . . .6 fig 5. pfc block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 fig 6. application diagram of UBA2013L/3 . . . . . . . . . .14 fig 7. package outline sot109-1 (so16) . . . . . . . . . . .16 fig 8. state diagram and state transitions . . . . . . . . . . .17 free datasheet http:///
draft draft draft dr draft draft draft dr af draft draft dr aft draft dra f t d draft draft draft draft dr aft draft dra nxp semiconductors uba2013/l3 hb driver ic ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 february 2007 document identifier: UBA2013L_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 half bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 pfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 start-up state . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 half bridge oscillator . . . . . . . . . . . . . . . . . . . . . 4 7.3 oscillating state . . . . . . . . . . . . . . . . . . . . . . . . 4 7.4 preheat state . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.5 ignition state . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.6 burn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.7 capacitive mode protection . . . . . . . . . . . . . . . 6 7.8 stop function. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.9 end-of-life protection . . . . . . . . . . . . . . . . . . . . 7 7.10 non-oscillating state . . . . . . . . . . . . . . . . . . . . . 7 7.11 start-up state . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.12 stop state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.13 vddlow state . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.14 pfc function . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.15 vo-low condition . . . . . . . . . . . . . . . . . . . . . . . 8 7.16 state and transition diagrams . . . . . . . . . . . . . . 9 7.17 charge coupling . . . . . . . . . . . . . . . . . . . . . . . . 9 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 9 thermal characteristics . . . . . . . . . . . . . . . . . 11 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 application information. . . . . . . . . . . . . . . . . . 14 12.1 design equations . . . . . . . . . . . . . . . . . . . . . . 15 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 15 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 15 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.1 state diagram and state transitions . . . . . . . . 17 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.5 patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.6 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18 contact information . . . . . . . . . . . . . . . . . . . . 19 19 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 free datasheet http:///

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